Archive for the ‘VHDL’ Category

NOT gate

Sunday, January 6th, 2008

I will try to post my learning process in VHDL and Verilog here for future reference. My first code is a NOT gate. Input pin connected to a push button and output connected to a LED.

In Schematic it will be:
not gate schematic

VHDL:

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-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;
 
-- this is the entity
entity NOTGATE is
   port (
         IN: in std_logic;
         OUT: out std_logic);
end NOTGATE;
 
architecture RTL of NOTGATE is
 
begin
 
  OUT <= not IN;
 
end RTL;

Verilog:

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module NOTGATE(in,out);
input in;
output out; 
 
reg out;
 
always
 begin
  out <= ~in;
 end
endmodule