Archive for the ‘FPGA’ Category

NOT gate

Sunday, January 6th, 2008

I will try to post my learning process in VHDL and Verilog here for future reference. My first code is a NOT gate. Input pin connected to a push button and output connected to a LED.

In Schematic it will be:
not gate schematic

VHDL:

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-- import std_logic from the IEEE library
library IEEE;
use IEEE.std_logic_1164.all;
 
-- this is the entity
entity NOTGATE is
   port (
         IN: in std_logic;
         OUT: out std_logic);
end NOTGATE;
 
architecture RTL of NOTGATE is
 
begin
 
  OUT <= not IN;
 
end RTL;

Verilog:

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module NOTGATE(in,out);
input in;
output out; 
 
reg out;
 
always
 begin
  out <= ~in;
 end
endmodule

Bought Altera FPGA Development board

Saturday, January 5th, 2008

I bought an Altera FPGA development board from Ebay. It had to be shipped from HongKong to me so it took a few weeks. It arrived between christmas and new year.

Features:
1. DC 5V powered.
2. Cyclone chip: EP1C3T144C8 (QFP144).
3. Configuration chip: EPCS1 (1M).
4. Can work on JTAG or AS mode.
5. 6 digit 7-seg LED, 4×3 LED matrix, another single LED.
6. 4×3 Keys, 8-bit DIP Switches for input.
7. 20MHz oscillator for main clock.
8. 40-pin and 20-pin DIL connectors for IO interface.
9. Download Cable: ByteBlaster II.
10. Sample source code and Schematic (on CD).

The manufacturer of the board is TJQIDONG from China (Never heard of it to be honest ;) ).

The board looks a bit cheap. There was no real product package and the software CD was a burned Philips CDR. That’s not a big problem for me. Because this is my first FPGA experience a better documentation about how to get started with the Quartus II software and the board would be handy. Luckily they provided a full schematic of the board.

I can now config the FPGA through JTAG with a programming file of their demo software. I still have to figure out how to program the EPCS1 Config Chip.

fpga_development_board1.jpg

fpga_development_board2.jpg

fpga_byteblaster.jpg